fadd.

Floating Add (Record)

fadd. FRT,FRA,FRB

Adds the contents of two floating-point registers and places the result into another register.

Encoding

Binary Layout

63

0:5

FRT

6:10

FRA

11:15

FRB

16:20

00000

21:25

21

26:30

Rc

31

 

Format A-form

Opcode 0xFC00002A

Extension Floating-Point

Operands

• FRT
  Target FPR
• FRA
  Source FPR A
• FRB
  Source FPR B

Example

fadd f1, f2, f3

// f1 = f2 + f3

Registers Altered

FPSCR, CR1, CR0

Related

More in Floating-Point

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The floating-point operand in register FRA is added to the floating-point operand in register FRB. The result is rounded to the target precision under control of RN and placed into register FRT.

Operation

if 'fadd' then
    FRT <- (FRA) + (FRB)
else if 'fadd.' then
    FRT <- (FRA) + (FRB)
    CR1 <- result class and sign

Programming Note

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.