drrnd.

DFP Reround

drrnd. FRT,FRA,FRB,RMC

Rerounds a decimal floating-point number to the specified precision.

Encoding

Binary Layout

0

0:5

FRT

6:10

FRA

11:15

FRB

16:20

RMC

21:30

Rc

31

 

Format Z23-form

Opcode 0xEC000046

Extension Decimal Floating-Point

Operands

• FRT
  Target Floating-Point Register
• FRA
  Source Floating-Point Register containing the reference significance
• FRB
  Source Floating-Point Register containing the value to be rounded
• RMC
  Rounding Mode Control
• k
  Number of significant digits

Example

drrnd. r4, r5

Registers Altered

FPSCR, CR0

Related

More in Decimal Floating-Point

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Rerounds a decimal floating-point number from FRB to the precision specified by the rounding mode control, placing the result in FRA and setting CR1 based on the result (if Rc=1). The instruction handles overflow, underflow, and inexact exceptions according to FPSCR settings. This instruction requires Decimal Floating-Point support and modifies CR1 and FPSCR when Rc is set.

Operation

FRA ← dround(FRB, RMC)
if Rc = 1 then CR1 ← (FRA_exception_flags)

Programming Note

The drrnd instruction is used to reround a decimal floating-point number in register RA according to the rounding mode specified in the FPSCR. Ensure that the FPSCR's rounding mode is set appropriately before executing this instruction to achieve the desired precision. This instruction operates at user privilege level and does not raise exceptions under normal circumstances, but it may alter the contents of CR0 if an exception occurs during execution.