ddiv.

Decimal Divide (Record)

ddiv. FRT,FRA,FRB

Divides the contents of two decimal floating-point registers and places the result in a target register.

Encoding

Binary Layout

59

0:5

FRT

6:10

FRA

11:15

FRB

16:20

546

21:30

/

31

 

Format X-form

Opcode 0xEC000444

Extension Decimal Floating-Point

Operands

• FRT
  Target
• FRA
  Src A
• FRB
  Src B

Example

ddiv f1, f2, f3

Registers Altered

FPSCR, CR1

Related

More in Decimal Floating-Point

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The DFP operand in FRA is divided by the DFP operand in FRB. The result is rounded to the target-format precision under control of the DRN (bits 29:31 of the FPSCR). An appropriate form of the rounded result is selected based on the ideal exponent and is placed in FRT.

Operation

if 'ddiv' then
    FRT <- (FRA) / (FRB)
    if Rc=1 then
        CR1 <- result of comparison

Programming Note

The ddiv instruction performs a decimal division, rounding the result according to the precision control bits in FPSCR. Ensure that operands are properly aligned and check for division by zero or overflow conditions, which may trigger exceptions. The result can be compared if Rc is set, updating CR1 accordingly.