dcmpu

Decimal Compare Unordered

dcmpu BF, FRA, FRB

Compares two DFP operands and sets the CR field to indicate the result.

Encoding

Binary Layout

0:5

6:10

FRA

11:15

FRB

16:20

21:25

26:29

Format X-form

Opcode 0xEC000504

Extension Decimal Floating-Point

Operands

BF
CR Field
FRA
Src A
FRB
Src B

Example

dcmpu cr0, f2, f3

Registers Altered

CR, FPSCR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Compares two decimal floating-point numbers and updates the specified condition register field. The comparison treats quiet NaNs as unordered (unlike ordered compare). The result sets the Less Than, Greater Than, Equal, or Unordered bits in the target CR field. No other status flags are affected.

Operation

if FRA is NaN or FRB is NaN then
  CR[BF] ← 0b0001  (Unordered)
else if FRA < FRB then
  CR[BF] ← 0b1000  (Less Than)
else if FRA > FRB then
  CR[BF] ← 0b0100  (Greater Than)
else
  CR[BF] ← 0b0010  (Equal)

Programming Note

The dcmpu instruction is used to compare two decimal floating-point numbers. It sets the condition register field BF based on the comparison result, which can be less than (FL), greater than (FG), equal to (FE), or unordered (FU) if either operand is NaN. Ensure that both operands are properly aligned and valid DFP values to avoid undefined behavior.