hrfid

Hypervisor Return From Interrupt Doubleword

hrfid

Returns from a hypervisor interrupt.

Encoding

Binary Layout

19

0:5

/

6:10

/

11:15

/

16:20

274

21:30

/

31

 

Format XL-form

Opcode 0x4C000224

Extension Privileged

Operands

Registers Altered

SRR0, SRR1, MSR

Related

More in Privileged

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Returns from a hypervisor interrupt by restoring the program counter from HSRR0 and machine state from HSRR1, then resuming execution at the restored address. This is a hypervisor-privileged instruction and only valid when the processor is in hypervisor state. It acts as a serializing instruction.

Operation

NIA ← HSRR0
Restore MSR from HSRR1
Return

Programming Note

The hrfid instruction is crucial for hypervisors to manage interrupt returns, updating the MSR and setting the NIA based on values from HSRR. Ensure that HSRR registers are correctly populated before executing hrfid to avoid undefined behavior. This instruction operates at supervisor level and may trigger exceptions if executed in an inappropriate context.