vadduhm

Vector Add Unsigned Halfword Modulo

vadduhm vD, vA, vB

Adds 8 halfwords modulo 65536.

Details

The Vector Add Unsigned Halfword Modulo instruction adds corresponding unsigned halfword elements from two source vectors and places the results in a destination vector. The addition is performed modulo, meaning that if the sum exceeds the maximum value for an unsigned halfword (65535), it wraps around to zero.

Pseudocode Operation

if MSR.VEC=0 then Vector_Unavailable()
do i = 0 to 7
   src1 ←EXTZ(VSR[VRA+32].hword[i])
   src2 ←EXTZ(VSR[VRB+32].hword[i])
   VSR[VRT+32].hword[i] ←CHOP16(src1 + src2)
end

Programming Note

This instruction is commonly used for vectorized addition of unsigned 16-bit integers with modulo behavior, useful in applications like image processing or cryptography. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation processes each halfword element independently, so there are no ordering requirements between elements, but alignment of input vectors to 16-byte boundaries can improve performance.

Example

vadduhm vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
64
21
 
Format VX-form
Opcode 0x10000040
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B