vadduhm

Vector Add Unsigned Halfword Modulo

vadduhm vD, vA, vB

Adds 8 halfwords modulo 65536.

Details

Adds eight pairs of unsigned halfword elements from vA and vB with modulo 65536 arithmetic (overflow wraps around) and stores the results in vD. This VMX instruction does not affect condition or status registers and operates in modulo mode without saturation.

Pseudocode Operation

vD[0:15] ← (vA[0:15] + vB[0:15]) mod 2^16
vD[16:31] ← (vA[16:31] + vB[16:31]) mod 2^16
vD[32:47] ← (vA[32:47] + vB[32:47]) mod 2^16
vD[48:63] ← (vA[48:63] + vB[48:63]) mod 2^16
vD[64:79] ← (vA[64:79] + vB[64:79]) mod 2^16
vD[80:95] ← (vA[80:95] + vB[80:95]) mod 2^16
vD[96:111] ← (vA[96:111] + vB[96:111]) mod 2^16
vD[112:127] ← (vA[112:127] + vB[112:127]) mod 2^16

Programming Note

This instruction is commonly used for vectorized addition of unsigned 16-bit integers with modulo behavior, useful in applications like image processing or cryptography. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation processes each halfword element independently, so there are no ordering requirements between elements, but alignment of input vectors to 16-byte boundaries can improve performance.

Example

vadduhm vd, va, vb

Encoding

Binary Layout

Format VX-form

Opcode 0x10000040

Extension VMX (AltiVec)

Registers Altered MSR

Operands

vD
Target
vA
Src A
vB
Src B