xvf16ger2pn

VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Negative accumulate

xvf16ger2pn

Performs a rank-2 update of an accumulator register using 16-bit floating-point outer product, with positive multiply and negative accumulate.

Details

The xvf16ger2pn instruction computes a rank-2 General Exterior-product Register (GER) update using 16-bit floating-point operands. It multiplies pairs of 16-bit floating-point elements from two VSX vector registers with a positive sign, then subtracts (negative accumulate) the resulting outer product from the destination accumulator register. This instruction is part of the MMA (Matrix Multiply Assist) extension introduced in PowerISA v3.1.

Pseudocode Operation

Not available in specification

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.

Example

xvf16ger2pn

Encoding

Binary Layout
59
0
AT
6
/
9
XA
11
XB
16
146
21
AX
29
BX
30
/
31
 
Format XX3-form
Opcode 0x7E000000
Extension MMA

Operands