xvf16ger2pn

VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Negative accumulate

xvf16ger2pn AT,XA,XB

Performs a rank-2 update of an accumulator register using 16-bit floating-point outer product, with positive multiply and negative accumulate.

Encoding

Binary Layout
59
0:5
AT
6:8
/
9:10
XA
11:15
XB
16:20
146
21:28
AX
29
BX
30
/
31
 
Format XX3-form
Opcode 0xEC000490
Extension MMA

Operands

  • AT
    Accumulator target index (specifies which accumulator register in the range ACC0-ACC7)
  • XA
    Source VSX register containing 2 16-bit floating-point elements
  • XB
    Source VSX register containing 2 16-bit floating-point elements
  • AX
    Accumulator mask for rows (2 16-bit FP values, positive multiply)
  • BX
    Source mask for columns (2 16-bit FP values, negative accumulate)

Example

xvf16ger2pn

Related

More in MMA

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs a VSX rank-2 generalized matrix multiply (GER) update using 16-bit floating-point elements with positive multiply and negative accumulate semantics. The instruction computes an outer product of two 2-element vectors and subtracts the result from the target accumulator. This is an MMA extension instruction that updates a 2×2 block of the accumulator.

Operation

acc ← acc - (outer product of 2 16-bit FP elements from XA and 2 from XB)

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.