vshasigmad

Vector SHA-512 Sigma Doubleword

vshasigmad vD, vA, ST, SIX

Performs the SHA-512 σ0, σ1, Σ0, or Σ1 functions on doubleword elements of vector registers.

Encoding

Binary Layout

1730

0:5

VRT

6:10

VRA

11:15

16:20

SIX

21:31

Format VX-form

Opcode 0x100006C2

Extension Vector Crypto

Operands

vD
Target
vA
Source
ST
Type
SIX
Shift
VRT
Target Vector Register
VRA
Source Vector Register

Example

vshasigmad vd, va, r4, 0

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vshasigmad, the instruction performs either a SHA-512 σ0, σ1, Σ0, or Σ1 function on each doubleword element of VSR[VRA+32] based on the values in ST and SIX. The result is placed into corresponding elements of VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    src ← VSR[VRA+32].dword[i]
    if ST=0 & SIX.bit[2×i]=0 then
        // SHA-512 σ0 function
        VSR[VRT+32].dword[i] ← (src >>> 1) ⊕ (src >>> 8) ⊕ (src >> 7)
    if ST=0 & SIX.bit[2×i]=1 then
        // SHA-512 σ1 function
        VSR[VRT+32].dword[i] ← (src >>> 19) ⊕ (src >>> 61) ⊕ (src >> 6)
    if ST=1 & SIX.bit[2×i]=0 then
        // SHA-512 Σ0 function
        VSR[VRT+32].dword[i] ← (src >>> 28) ⊕ (src >>> 34) ⊕ (src >>> 39)
    if ST=1 & SIX.bit[2×i]=1 then
        // SHA-512 Σ1 function
        VSR[VRT+32].dword[i] ← (src >>> 14) ⊕ (src >>> 18) ⊕ (src >>> 41)
end

Programming Note

Bits 1 and 3 of SIX are reserved.