lxvx

Load VSX Vector Indexed X-form

lxvx XT,RA,RB

Loads a quadword from memory into a VSX register.

Encoding

Binary Layout

31

0:5

XT

6:10

RA

11:15

RB

16:20

268

21:30

TX

31

 

Format X-form

Opcode 0x7C000218

Extension VSX

Operands

• XT
  Target VSX Register
• RA
  Source General Purpose Register
• RB
  Source General Purpose Register
• xT
  Target Vector-Scalar Register
• rA
  Index General Purpose Register
• rB
  Base Address General Purpose Register

Example

lxvx vs1, r4, r5

Registers Altered

MSR

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Loads a 128-bit quadword from memory into a VSX register using indexed addressing. The effective address is computed as RA|0 + RB. No status fields are modified by this instruction.

Operation

EA ← (RA=0 ? 0 : GPR[RA]) + GPR[RB]
VSR[XT] ← MEM(EA, 16)

Programming Note

The lxvx instruction is used to load vector data from memory into VSX registers.