mfvsrwz

Move From VSR Word and Zero

mfvsrwz RA, XS

Moves the contents of a word element from a vector-scalar register to a general-purpose register, zeroing the upper bits.

Details

The contents of word element 1 of VSR[XS] are placed into bits 32:63 of GPR[RA]. The contents of bits 0:31 of GPR[RA] are set to 0. Let XS be the value 32×SX + S.

Pseudocode Operation

if SX=0 & MSR.FP=0 then FP_Unavailable()
if SX=1 & MSR.VEC=0 then Vector_Unavailable()
GPR[RA] ←EXTZ64(VSR[32×SX+S].word[1])

Programming Note

For SX=0, mfvsrwz is treated as a Floating-Point instruction in terms of resource availability. For SX=1, mfvsrwz is treated as a Vector instruction in terms of resource availability.

Extended Mnemonics

Extended Mnemonic Equivalent Instruction
mffprwz
mfvrwz

Example

mfvsrwz r4, vs1

Encoding

Binary Layout
31
0
XS
6
RA
11
0
16
115
 
Format XX1-form
Opcode 0x7C000073
Extension VSX
Registers Altered MSR

Operands

  • RA
    Target GPR
  • XS
    Source VSR