dcbz

Data Cache Block Set to Zero

dcbz RA, RB

Zeros out an entire cache block (usually 128 bytes) in memory. Critical for optimizing memory clears (memset).

Details

Data cache instruction that writes zeros to an entire cache block (typically 128 bytes) in memory at the effective address formed by RA + RB. The block is zero-filled and typically written back or marked clean in the cache. This is a memory hint instruction; no general-purpose registers are modified and no condition flags are affected.

Pseudocode Operation

EA ← (RA) + (RB)
block_start ← EA & ~(cache_block_size - 1)
for addr in block_start to block_start + cache_block_size - 1 step word_size do
  [addr] ← 0
end for

Programming Note

dcbz does not cause the block to exist in the data cache if the block is in storage that is Caching Inhibited. For storage that is neither Write Through Required nor Caching Inhibited, dcbz provides an efficient means of setting blocks of storage to zero. It can be used to initialize large areas of such storage, in a manner that is likely to consume less memory bandwidth than an equivalent sequence of Store instructions. For storage that is either Write Through Required or Caching Inhibited, dcbz is likely to take significantly longer to execute than an equivalent sequence of Store instructions.

Example

dcbz 0, r3

// Zero the cache line at address in r3.

Encoding

Binary Layout
31
0
/
6
RA
11
RB
16
1014
/
 
Format X-form
Opcode 0x7C0007EC
Extension Base

Operands

  • RA
    Base Address
  • RB
    Index Address