vdivesq

Vector Divide Extended Signed Quadword

vdivesq VRT,VRA,VRB

Divides the contents of two vector registers and updates the destination register with the quotient.

Details

For vdivesq, the signed integer value in VSR[VRA+32] concatenated with 128 0s is divided by the signed integer value in VSR[VRB+32]. The quotient is placed into VSR[VRT+32].

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()

dividend ← EXTS(VSR[VRA+32]) << 128
divisor ← EXTS(VSR[VRB+32])
VSR[VRT+32] ← CHOP128(dividend ÷ divisor)

Programming Note

This instruction is used for dividing a signed quadword value by another signed quadword value. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The operation involves extending the sign of the operands and handling division with potential overflow or zero divisor scenarios carefully.

Example

vdivesq v1, v2, v3

Encoding

Binary Layout
0
4
VRT
6
VRA
11
VRB
16
 
Format VX-form
Opcode 0x1000030B
Extension VMX (AltiVec)
Registers Altered None

Operands

  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register