pmxvf64ger

Prefixed Masked VSX Vector Float64 GER

pmxvf64ger AT, XA, XB, XMSK, YMSK

Masked version of Double-Precision MMA.

Details

Prefixed masked version of the 64-bit floating-point matrix multiply-accumulate (MMA) instruction. Performs a rank-1 update of a 4×4 matrix accumulator using masked 64-bit floating-point elements, where XMSK controls which columns of XA participate and YMSK controls which rows of XB participate. No condition register or status flags are affected; this is a privileged MMA extension instruction.

Pseudocode Operation

for i in 0..1:
  for j in 0..1:
    if (XMSK[i] == 1) & (YMSK[j] == 1):
      AT[i][j] ← AT[i][j] + (XA[i] × XB[j]) (FP64 × FP64 → FP64)

Programming Note

The pmxvf64ger instruction is useful for performing masked outer product accumulation on floating-point vectors. Ensure that the mask registers XMSK and YMSK are correctly set to control which elements of the input vectors XAp and XB participate in the computation. This instruction operates at a privilege level that allows access to VSX (Vector Scalar Extensions) and requires proper alignment of the input and accumulator vectors for optimal performance.

Example

pmxvf64ger acc0, vs2, vs3, 15, 15

Encoding

Binary Layout
1
0
3
6
PMSK
8
XMSK
9
YMSK
14
0
32
59
38
AT
41
/
43
XA
48
XB
53
19
56
AX
57
BX
58
/
 
Format MMIRR-form
Opcode 0x06000000
Extension Prefixed

Operands

  • AT
    Accumulator
  • XA
    Src A
  • XB
    Src B
  • XMSK
    Mask A
  • YMSK
    Mask B