adde

Add Extended

adde RT, RA, RB

Adds two registers plus the current Carry bit.

Encoding

Binary Layout

31

0:5

RT

6:10

RA

11:15

RB

16:20

OE

21

138

22:30

Rc

31

 

Format XO-form

Opcode 0x7C000114

Extension Base

Operands

• RT
  Target Register
• RA
  Source Register 1
• RB
  Source Register 2

Example

adde r3, r4, r5

// r3 = r4 + r5 + CA

Registers Altered

CR0

Related

Across architectures

Add With Carry : how x86, ARM, RISC-V, and PowerISA each do this.

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Adds the values in registers RA and RB plus the Carry bit from XER and places the result in RT. If OE=1, sets XER[SO] and XER[OV] on signed overflow. If Rc=1, updates CR0 based on the result. This instruction is used for multi-precision arithmetic.

Operation

RT ← RA + RB + XER[CA]
if OE = 1 then
  if overflow then XER[OV] ← 1; XER[SO] ← 1
if result > 2^64-1 or result < -2^64 then XER[CA] ← 1 else XER[CA] ← 0
if Rc = 1 then
  CR0 ← (RT < 0) || (RT > 0) || (RT = 0) || XER[SO]

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.