addc

Add Carrying

addc RT,RA,RB

Adds the contents of two registers and a carry bit, placing the result in a target register.

Encoding

Binary Layout

31

0:5

RT

6:10

RA

11:15

RB

16:20

OE

21

10

22:30

Rc

31

 

Format XO-form

Opcode 0x7C000014

Extension Base

Operands

• RT
  Target Register
• RA
  Source Register 1
• RB
  Source Register 2

Example

addc r3, r4, r5

// r3 = r4 + r5 (Updates Carry)

Registers Altered

CR0, XER

Related

Across architectures

Add With Carry : how x86, ARM, RISC-V, and PowerISA each do this.

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The sum (RA) + (RB) is placed into register RT.

Operation

if 'addc' then
    RT <- (RA) + (RB)
else if 'addc.' then
    RT <- (RA) + (RB)
    if Rc=1 then update CR0
else if 'addco' then
    RT <- (RA) + (RB)
    if OE=1 then update XER[SO], XER[OV]
else if 'addco.' then
    RT <- (RA) + (RB)
    if Rc=1 then update CR0
    if OE=1 then update XER[SO], XER[OV]

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.