xscvhpdp

VSX Scalar Convert Half-Precision to Double-Precision format XX2-form

xscvhpdp XT, XB

Converts a half-precision floating-point value to a double-precision floating-point value.

Details

The instruction converts the half-precision floating-point value in the rightmost halfword of doubleword element 0 of VSR[XB] to a double-precision floating-point value and places it into doubleword element 0 of VSR[XT]. Doubleword element 1 of VSR[XT] is set to 0.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()
reset_flags()
src ←bfp_CONVERT_FROM_BFP16(VSR[BX×32+B].hword[3])
if src.class.SNaN=1 then
    result ←bfp64_CONVERT_FROM_BFP(bfp_QUIET(src))
else
    result ←bfp64_CONVERT_FROM_BFP(src)
vxsnan_flag ←src.class.SNaN
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
vex_flag ←FPSCR.VE & vxsnan_flag
if vex_flag=0 then do
    VSR[TX×32+T].dword[0] ←result
    VSR[TX×32+T].dword[1] ←0x0000_0000_0000_0000
    FPSCR.FPRF ←fprf_CLASS_BFP64(result)
end
FPSCR.FR ←0
FPSCR.FI ←0

Programming Note

Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.

Example

xscvhpdp vs1, vs3

Encoding

Binary Layout
T
0
16
6
B
11
347
16
BX TX
21
 
Format XX2-form
Opcode 0xF0000158
Extension VSX
Registers Altered FPSCR, FPRF, FX, VXSNAN

Operands

  • XT
    Target
  • XB
    Source