plq

Prefixed Load Quadword

plq RTp, D(RA), R

Loads 128 bits into two GPRs using a 34-bit offset.

Encoding

Binary Layout

1

0:5

2

6:7

R

8

0

9:13

D0

14:31

56

32:37

RT

38:42

RA

43:47

D1

48:63

 

Format MLS:D-form

Opcode 0x04000000E0000000

Extension Prefixed

Operands

• RTp
  Target Pair
• D
  Offset
• RA
  Base
• R
  PC-Rel

Example

plq r4, 0(r4), 0

Related

More in Prefixed

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Prefixed load of 128 bits from memory into two consecutive general-purpose registers (RT and RT+1) using a 34-bit signed offset. The effective address is computed as RA + D (if R=0) or the prefixed address. This is a prefixed instruction requiring the Prefixed extension; no condition register or status flags are affected.

Operation

if RA = 0 then
  EA ← D
else
  EA ← (RA) + D
RT ← [EA]
RT+1 ← [EA+8]

Programming Note

The plq instruction is used to load a quadword from memory into an even-odd pair of GPRs. Ensure that the effective address (EA) is properly aligned to 16 bytes for optimal performance and to avoid alignment exceptions. This instruction operates at the problem state privilege level, so it cannot be executed in supervisor or hypervisor states.