plq

Prefixed Load Quadword

plq RTp, D(RA), R

Loads 128 bits into two GPRs using a 34-bit offset.

Details

The plq instruction loads a quadword from storage into an even-odd pair of GPRs. Independent of the endian mode, the even-numbered GPR is loaded with the doubleword from storage addressed by EA, and the odd-numbered GPR is loaded with the doubleword addressed by EA+8.

Pseudocode Operation

if ‘‘plq’’ & R=0 then
    EA ←(RA|0) + EXTS64(d0||d1)
if ‘‘plq’’ & R=1 then
    EA ←CIA + EXTS64(d0||d1)
if Big-Endian byte ordering then
    RTp||RTp+1 ←MEM(EA,16)
if ‘‘plq’’ and Little-Endian byte ordering then
    RTp+1||RTp ←MEM(EA,16)

Programming Note

The plq instruction is used to load a quadword from memory into an even-odd pair of GPRs. Ensure that the effective address (EA) is properly aligned to 16 bytes for optimal performance and to avoid alignment exceptions. This instruction operates at the problem state privilege level, so it cannot be executed in supervisor or hypervisor states.

Example

plq r4, 0(r4), 0

Encoding

Binary Layout
1
0
2
6
R
8
0
9
D0
14
56
32
RT
38
RA
43
D1
48
 
Format MLS:D-form
Opcode 0x06000000
Extension Prefixed

Operands

  • RTp
    Target Pair
  • D
    Offset
  • RA
    Base
  • R
    PC-Rel