vpkuhus

Vector Pack Unsigned Halfword Unsigned Saturate

vpkuhus vD, vA, vB

Saturates 8 halfwords to 16 unsigned bytes.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

142

21:31

Format VX-form

Opcode 0x1000008E

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B

Example

vpkuhus vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Packs and saturates eight unsigned halfword elements from vA and vB into sixteen unsigned bytes in vD, discarding or saturating values that exceed 255. The saturation flag in VSCR is set if any saturation occurred. This VMX instruction operates in saturating mode for unsigned values.

Operation

for i in 0 to 3:
  vD[2*i:2*i+7] ← Saturate_UH_to_UB(vA[16*i:16*i+15])
  vD[2*i+8:2*i+15] ← Saturate_UH_to_UB(vB[16*i:16*i+15])
if any saturation occurred:
  VSCR[SAT] ← 1

Programming Note

The vpkuhus instruction is used to pack unsigned halfwords from two source vectors into a destination vector, with saturation applied if the values exceed 8 bits. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The operation processes each halfword from the input vectors and clamps the result to fit within an 8-bit unsigned integer range.