vpkuhum

Vector Pack Unsigned Halfword Unsigned Modulo

vpkuhum vD, vA, vB

Packs the upper half of each 16-bit element from two vector registers into a single byte in another vector register.

Details

The instruction packs the upper half of each 16-bit element from VSR[VRA+32] and VSR[VRB+32] into the corresponding byte elements of VSR[VRT+32].

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
else
    vsrc.qword[0] ← VSR[VRA+32]
    vsrc.qword[1] ← VSR[VRB+32]
    for i = 0 to 15 do
        VSR[VRT+32].byte[i] ← vsrc.hword[i].bit[8:15]
    end
end

Programming Note

This instruction is used to pack the upper half of each 16-bit element from two source vectors into a destination vector. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set before using this instruction; otherwise, it will raise an exception. The operation processes 32 bytes (16 elements) from each source vector and packs them into the destination vector, maintaining the upper half of each element. This instruction does not require any specific alignment but must be executed in a privileged context where the VEC bit is enabled.

Example

vpkuhum vd, va, vb

Encoding

Binary Layout
18
0
VRT
6
VRA
11
VRB
16
14
21
 
Format VX-form
Opcode 0x1000000E
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register