cfuged

Centrifuge Doubleword

cfuged RA, RS, RB

Separates bits of the source register into two groups based on a mask (Power10 Scalar).

Encoding

Binary Layout

0:5

6:10

11:15

16:20

21:30

Format X-form

Opcode 0x7C0001B8

Extension Base

Operands

RA
Target
RS
Source
RB
Mask

Example

cfuged r4, r3, r5

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Centrifuges a 64-bit doubleword by separating bits according to a mask RB, moving masked bits to the low order of the result and unmasked bits to the high order (Power10 Scalar). The result is placed in RA. No CR, XER, or FPSCR fields are affected.

Operation

do_mask ← RB; result_low ← []; result_high ← []; j_low ← 0; j_high ← 0; for i in 0 to 63 do; if (do_mask[i] = 1) then result_low[j_low] ← RS[i]; j_low ← j_low + 1; else result_high[j_high] ← RS[i]; j_high ← j_high + 1; RA ← result_low || result_high;

Programming Note

The cfuged instruction is useful for counting leading zeros in a doubleword value, but only considering the bits that are set to 1 in a mask. Ensure the mask register (RB) has bits set where you want to consider leading zeros in the source register (RS). The result is zero-extended to 64 bits before being stored in the destination register (RA). This instruction operates at user privilege level and does not generate exceptions under normal conditions.