rlwnm.

Rotate Left Word Then AND with Mask (Record)

rlwnm. RT,RS,RB,MB,ME

Rotates the contents of register RS left by the number of bits specified by (RB)59:63, and then performs a bitwise AND operation with a mask.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

21:25

26:30

Format M-form

Opcode 0x5C000000

Extension Base

Operands

RA
Target
RS
Source
RB
Shift Reg
MB
Mask Begin
ME
Mask End
RT
Target General Purpose Register

Example

rlwnm r3, r3, r5, 0, 31

Registers Altered

CR0

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The contents of register RS are rotated 32 left the number of bits specified by (RB)59:63. A mask is generated having 1-bits from bit MB+32 through bit ME+32 and 0-bits elsewhere. The rotated data are ANDed with the generated mask and the result is placed into register RA.

Operation

if 'rlwnm' then
    n ← (RB)59:63
    r ← ROTL32((RS)32:63, n)
    m ← MASK(MB+32, ME+32)
    RA ← r & m
else if 'rlwnm.' then
    n ← (RB)59:63
    r ← ROTL32((RS)32:63, n)
    m ← MASK(MB+32, ME+32)
    RA ← r & m

Extended Mnemonics

Extended Mnemonic	Equivalent Instruction
rotlw
rotlw.

Programming Note

RS, with the bits numbered from 0 through 31. rlwnm can be used to extract an n-bit field that starts at variable bit position b in RSL, right-justified into the low-order 32 bits of register RA (clearing the remaining 32-n bits of the low-order 32 bits of RA), by setting RB59:63=b+n, MB=32-n, and ME=31. It can be used to extract an n-bit field that starts at variable bit position b in RSL, left-justified into the low-order 32 bits of register RA (clearing the remaining 32-n bits of the low-order 32 bits of RA), by setting RB59:63=b, MB = 0, and ME=n-1. It can be used to rotate the contents of the low-order 32 bits of a register left (right) by variable n bits, by setting RB59:63=n (32-n), MB=0, and ME=31.