srad.
Shift Right Algebraic Doubleword
srad. RT,RA,RB
Shifts the contents of a doubleword register right algebraically, shifting in sign bits.
Encoding
Binary Layout
31
0:5
RS
6:10
RA
11:15
RB
16:20
794
21:30
Rc
31
Operands
-
RT
Target General Purpose Register -
RA
Source General Purpose Register -
RB
Source General Purpose Register
Reference
View in PowerISA v3.1C Specification ↗
OPF Power ISA v3.1C
Description
The contents of register RA are shifted right by the number of bits specified by the low-order 7 bits of register RB. Bits shifted out of position 63 are lost. Sign bits are shifted into the high-order bits, replicating the sign bit (RA[0]). If the shift amount is greater than 63, each bit of the result is equal to the sign bit of RA. The XER[CA] bit is set if the result is negative and any '1' bits are shifted out; otherwise XER[CA] is cleared. If the Rc bit is set, CR0 is updated.
Operation
n ← rB[58:63]
if rB[57] = 0 then
r ← ROTL64(rA, 64-n)
mask ← MASK(n, 63)
rT ← r & mask | (64)rA[0] & ¬mask
else
rT ← (64)rA[0]
XER[CA] ← rA[0] & (rT ≠ rA)
XER[CA32] ← rA[0] & (rT[32:63] ≠ rA[32:63])Programming Note
The srad. instruction is commonly used for right-shifting signed integers while preserving the sign bit. Be cautious with shift amounts greater than 63, as they result in a full replication of the sign bit. The XER[CA] flag indicates if negative bits were shifted out, which can be useful for overflow detection. Ensure that register RB contains a valid shift amount to avoid unexpected results.