xvi16ger2s

VSX Vector Integer 16-bit GER (Rank-2 Update) Saturate

xvi16ger2s AT, XA, XB

Performs a vectorized signed integer multiply and accumulate operation with saturation.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

AXBX

21:31

Format XX3-form

Opcode 0xEC000158

Extension MMA

Operands

AT
Accumulator
XA
Src A
XB
Src B

Example

xvi16ger2s acc0, vs2, vs3

Registers Altered

VSCR, VSX registers

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction performs a vectorized signed integer multiply and accumulate operation with saturation. It multiplies the elements of two vectors and accumulates the results into a destination vector, saturating any overflow values.

Operation

if MSR.VSX=0 then VSX_Unavailable()

PMSK ←0b11
XMSK ←0b1111
YMSK ←0b1111
sat_flag ←0

do i = 0 to 3
do j = 0 to 3
   if XMSK.bit[i] & YMSK.bit[j] then do
      prod0 ←(PMSK.bit[0]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].hword[0]) * EXTS(VSR[32×BX+B].word[j].hword[0])
      prod1 ←(PMSK.bit[1]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].hword[1]) * EXTS(VSR[32×BX+B].word[j].hword[1])

      psum ←prod0 + prod1

      ACC[AT][i].word[j] ←si32_CLAMP( psum )

      if sat_flag=1 then VSCR.SAT ←1
   end
   else
      ACC[AT][i][j] ←0x0000_0000
end
end

Programming Note

This instruction is commonly used for vectorized operations involving 16-bit integer multiplication and accumulation with saturation. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. Be cautious of overflow conditions, as they will be saturated, which might affect the precision of your results. The instruction operates on 128-bit vectors, so ensure proper alignment for optimal performance.