xscvqpdp

VSX Scalar Convert Quad-Precision to Double

xscvqpdp vD, vB

Converts a quad-precision floating-point value to a double-precision floating-point value with round-to-even rounding.

Encoding

Binary Layout

1

0:5

VRT

6:8

0

9

VRB

10

RO

11:15

0

16:20

0

21:30

0

31

 

Format X-form

Opcode 0xFC140688

Extension VSX

Operands

• vD
  Target
• vB
  Source
• VRT
  Target Vector Register
• VRB
  Source Vector Register

Example

xscvqpdp vd, vb

Registers Altered

FPSCR, FPRF, FR, FI, VXSNAN, OX, UX, XX

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Converts a 128-bit quad-precision floating-point value in VSR vB to a 64-bit double-precision floating-point value, placing the result in the low 64 bits of VSR vD using round-to-even rounding. FPSCR exception flags (XX, ZX, OX, UX) are updated based on the conversion result. Requires VSX support.

Operation

vD[0:63] ← ConvertQuadPrecisionToDoublePrecision(vB[0:127])
FPSCR[XX,ZX,OX,UX] ← updated based on conversion result

Programming Note

This instruction is used to convert a quad-precision floating-point number to a double-precision floating-point number. Ensure that the VSX facility is enabled in the MSR register, as attempting to use this instruction when VSX is unavailable will result in an exception. The conversion respects the rounding mode specified in the FPSCR register, and any exceptions such as invalid operation (VXSNAN), overflow (OX), underflow (UX), or inexact (XX) are recorded in the FPSCR. The result is stored in the first doubleword of the destination vector register, with the second doubleword set to zero.