xscvqpdp

VSX Scalar Convert Quad-Precision to Double

xscvqpdp vD, vB

Converts a quad-precision floating-point value to a double-precision floating-point value with round-to-even rounding.

Details

The xscvqpdp instruction converts the quad-precision floating-point value in VSR[VRB+32] to a double-precision floating-point value and places it into doubleword element 0 of VSR[VRT+32]. The contents of doubleword element 1 of VSR[VRT+32] are set to 0.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src ← bfp_CONVERT_FROM_BFP128(VSR[VRB+32])
rnd ← bfp_ROUND_TO_BFP64(RO, FPSCR.RN, src)
result ← bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
if xx_flag=1 then SetFX(FPSCR.XX)
vex_flag ← FPSCR.VE & vxsnan_flag
if vex_flag=0 then do
    VSR[VRT+32].dword[0] ← result
    FPSCR.FPRF ← fprf_CLASS_BFP64(result)
end
FPSCR.FR ← (vxsnan_flag=0) & inc_flag
FPSCR.FI ← (vxsnan_flag=0) & xx_flag

Programming Note

This instruction is used to convert a quad-precision floating-point number to a double-precision floating-point number. Ensure that the VSX facility is enabled in the MSR register, as attempting to use this instruction when VSX is unavailable will result in an exception. The conversion respects the rounding mode specified in the FPSCR register, and any exceptions such as invalid operation (VXSNAN), overflow (OX), underflow (UX), or inexact (XX) are recorded in the FPSCR. The result is stored in the first doubleword of the destination vector register, with the second doubleword set to zero.

Example

xscvqpdp vd, vb

Encoding

Binary Layout
1
0
VRT
16
0
21
VRB
26
RO
30
0
31
0
0
 
Format X-form
Opcode 0xFC000688
Extension VSX
Registers Altered FPSCR, FPRF, FR, FI, VXSNAN, OX, UX, XX

Operands

  • vD
    Target
  • vB
    Source
  • VRT
    Target Vector Register
  • VRB
    Source Vector Register