lvehx

Load Vector Element Halfword Indexed X-form

lvehx VX,RA,RB

Loads a halfword element from memory into the corresponding halfword element of a vector register, with the address computed as the sum of RA and RB, aligned to a halfword boundary.

Encoding

Binary Layout

31

0:5

VRT

6:10

RA

11:15

RB

16:20

39

21:30

/

31

 

Format X-form

Opcode 0x7C00004E

Extension VMX (AltiVec)

Operands

• VX
  Target VSX Register
• RA
  Base Address General Purpose Register
• RB
  Index General Purpose Register

Example

lvehx v1, r4, r5

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Loads a halfword (16-bit) element from memory at the address formed by RA + RB into the corresponding halfword element of vector register VRT. The effective address is aligned to a halfword boundary. This is a VMX/AltiVec instruction with no effect on condition or status registers.

Operation

EA ← (RA) + (RB)
VRT[element] ← MEM(EA, 2)

Programming Note

The lvehx instruction loads a halfword from memory into a specific element of a vector register. Ensure the effective address is halfword-aligned to avoid alignment faults. The operation does not require any special privileges, but it may raise an exception if the access violates memory protection rules.