vavguw

Vector Average Unsigned Word

vavguw vD, vA, vB

Computes (a+b+1)/2 for words.

Encoding

Binary Layout

4

0:5

vD

6:10

vA

11:15

vB

16:20

1154

21:31

 

Format VA-form

Opcode 0x10000482

Extension VMX (AltiVec)

Operands

• vD
  Target
• vA
  Src A
• vB
  Src B

Example

vavguw vd, va, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Computes the average of corresponding unsigned words in vA and vB using rounding (vA + vB + 1) >> 1, storing the result in vD. This is a vector operation that processes 4 independent word elements in parallel. No condition flags or status fields are affected.

Operation

for i in 0 to 3 do
  vD[32*i:32*i+31] ← ((vA[32*i:32*i+31] + vB[32*i:32*i+31] + 1) >> 1)[31:0]
end for

Programming Note

The vavguw instruction is used to compute the average of unsigned word elements from two vectors. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set; otherwise, a Vector_Unavailable exception will be raised. This instruction processes each 32-bit word element independently, so alignment requirements are not strict. Be cautious with potential overflow when summing large unsigned integers.