vbpermq

Vector Bit Permute Quadword

vbpermq VRT,VRA,VRB

Performs a bit permutation on two vector registers and stores the result in another vector register.

Details

Performs a bit permutation on the 128-bit quadword formed by concatenating two vector registers. The bits of the concatenated source are rearranged according to indices in VRB, with the 64-bit result placed in the left doubleword of VRT and the right doubleword cleared. No condition registers or status fields are affected.

Pseudocode Operation

source ← VRA || VRB
result ← 0
for i in 0 to 63:
  bit_index ← VRB.doubleword[i][0:6]
  result[i] ← source[bit_index]
VRT[0].doubleword ← result
VRT[1].doubleword ← 0

Programming Note

The fact that the permuted bit is 0 if the corresponding index value exceeds 127 permits the permuted bits to be selected from a 256-bit quantity, using a single index register.

Example

vbpermq v1, v2, v3

Encoding

Binary Layout
1001
0
VRT
6
VRA
11
VRB
16
10000000000000000000000000000000
21
 
Format VX-form
Opcode 0x1000054C
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Index Source Vector Register