vmulesw

Vector Multiply Even Signed Word

vmulesw vD, vA, vB

Multiplies even-indexed signed words from two vector registers and stores the results in a destination vector register.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

392

21:31

Format VX-form

Opcode 0x10000388

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vmulesw vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vmulesw, each pair of even-indexed signed words from VSR[VRA+32] and VSR[VRB+32] are multiplied, and the 64-bit products are stored in VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    src1 ←EXTS(VSR[VRA+32].word[2×i])
    src2 ←EXTS(VSR[VRB+32].word[2×i])
    VSR[VRT+32].dword[i] ←CHOP64(src1 × src2)
end

Programming Note

This instruction multiplies even-indexed signed words from two vector registers and stores the 64-bit products in another register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. Be cautious of overflow, as the multiplication results are truncated to 64 bits.