xscvdpuxds

VSX Scalar Convert Double-Precision to Unsigned Doubleword with Round to Zero

xscvdpuxds XT, XB

Converts a double-precision floating-point value to an unsigned 64-bit integer using round towards zero.

Encoding

Binary Layout

0:5

6:10

11:15

328

16:20

21:25

26:31

Format XX2-form

Opcode 0xF0000520

Extension VSX

Operands

XT
Target
XB
Source

Example

xscvdpuxds vs1, vs3

Registers Altered

FPSCR (undefined), VXSNAN, VXCVI, FX, XX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction converts the double-precision floating-point value in doubleword element 0 of VSR[XB] to an unsigned 64-bit integer. The result is placed into doubleword element 0 of VSR[XT], and doubleword element 1 of VSR[XT] is set to 0.

Operation

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src ← bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
rnd ← bfp_ROUND_TO_INTEGER(0b001, src)
result ← ui64_CONVERT_FROM_BFP(rnd)
vxsnan_flag ← vxsnan(src)
vxcvi_flag ← vxcvi(src)
xx_flag ← xx(src)
vx_flag ← vxsnan_flag | vxcvi_flag
vex_flag ← FPSCR.VE & vx_flag
if vex_flag=0 then
do
    VSR[32×TX+T].dword[1] ← result
    VSR[32×TX+T].dword[2] ← 0x0000_0000_0000_0000
    FPSCR.FPRF ← 0bUUUUU
    FPSCR.FR ← inc_flag
    FPSCR.FI ← xx_flag
end
else
do
    FPSCR.FR ← 0b0
    FPSCR.FI ← 0b0
end

Programming Note

If src is a NaN, the result is 0x0000_0000_0000_0000 and VXCVI is set to 1. If src is an SNaN, VXSNAN is also set to 1. If the rounded value is greater than 264 -1, the result is 0xFFFF_FFFF_FFFF_FFFF and VXCVI is set to 1. Otherwise, if the rounded value is less than 0, the result is 0x0000_0000_0000_0000 and VXCVI is set to 1. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.