lbarx

Load Byte And Reserve Indexed

lbarx RT,RA,RB,EH

Loads a byte from memory and reserves the location for exclusive access.

Encoding

Binary Layout

31

0:5

RT

6:10

RA

11:15

RB

16:20

52

21:30

0

31

 

Format X-form

Opcode 0x7C000068

Extension Base

Operands

• RT
  Target
• RA
  Base
• RB
  Index
• EH
  Hint for subsequent store operation

Example

lbarx r3, r4, r5, 0

Registers Altered

RESERVE, RESERVE_LENGTH, RESERVE_ADDR

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Loads a single byte from memory at the address computed from RA+RB into RT, zero-extending to 64 bits, and reserves the location for exclusive access for a subsequent stbcx. instruction. The optional EH field provides a hint for the subsequent store. No condition register fields are affected by this load.

Operation

EA ← (RA|0) + RB
RT ← (56)0 || MEM[EA, 1]
RESERVED ← EA

Programming Note

lbarx serves as both a basic and an extended mnemonic. The Assembler will recognize a lbarx mnemonic with four operands as the basic form, and a lbarx mnemonic with three operands as the extended form. In the extended form the EH operand is omitted and assumed to be 0.