lbzcix

Load Byte and Zero Caching Inhibited Indexed

lbzcix RT,RA,RB

Loads a byte from memory into a register, zeroing the upper bits of the target register.

Encoding

Binary Layout

0

0:5

RT

6:10

RA

11:15

RB

16:31

 

Format X-form

Opcode 0x7C0006AA

Extension Base

Operands

• RT
  Target General Purpose Register
• RA
  Source General Purpose Register
• RB
  Source General Purpose Register

Example

lbzcix r3, r4, r5

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The effective address (EA) is calculated as the sum of RA and RB. The byte at EA is loaded into RT56:63, while RT0:55 are set to 0. The storage access is performed as though the location is Caching Inhibited and Guarded.

Operation

if RA = 0 then
    b ← 0
else
    b ← (RA)
EA ← b + (RB)
RT ← 560 || MEM(EA, 1)

Programming Note

The lbzcix instruction is useful for loading a single byte from memory into the upper bits of a register while zeroing out the lower bits. It ensures that the access is treated as caching inhibited and guarded, which can be crucial for accessing special memory regions. Be cautious with RA being zero, as it results in an effective address equal to RB, potentially leading to unintended memory accesses if not handled properly.