vminsb

Vector Minimum Signed Byte

vminsb vD, vA, vB

Compares the signed byte elements of two vector registers and stores the minimum values in a third vector register.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

1538

21:31

Format VA-form

Opcode 0x10000302

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vminsb vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vminsb, each byte element of VSR[VRA+32] is compared to the corresponding byte element of VSR[VRB+32]. The smaller value is stored in the corresponding byte element of VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 15
    src1 ← VSR[VRA+32].byte[i]
    src2 ← VSR[VRB+32].byte[i]
    lt_flag ← EXTS(src1) < EXTS(src2)
    VSR[VRT+32].byte[i] ← lt_flag=1 ? src1 : src2
end

Programming Note

This instruction is used to perform element-wise minimum comparison on signed byte values. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation respects the sign of the bytes, so it correctly handles negative numbers. There are no specific alignment requirements for the vector registers involved.