vmodsq

Vector Modulo Signed Quadword

vmodsq VRT,VRA,VRB

Performs signed modulo operation on quadword elements of two vector registers and stores the result in another vector register.

Details

The vmodsq instruction performs a signed modulo operation on the quadword elements of VSR[VRA+32] and VSR[VRB+32], storing the result in VSR[VRT+32].

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()

dividend ← EXTS(VSR[VRA+32])
divisor ← EXTS(VSR[VRB+32])

VSR[VRT+32] ← CHOP128(dividend % divisor)

Let src1 be the signed integer value in VSR[VRA+32].
Let src2 be the signed integer value in VSR[VRB+32].
The remainder of src1 divided by src2 is placed into VSR[VRT+32].
The remainder is the unique signed integer that satisfies
  quotient = dividend ÷ divisor
  remainder = dividend −(quotient × divisor)
where 0 ≤remainder < |divisor| if the dividend is nonnegative, and −|divisor| < remainder ≤0 if the dividend is negative.

If an attempt is made to perform any of the modulo operations
    0x8000_0000_0000_0000_0000_0000_0000_0000 % -1
then the contents of VSR[VRT+32] are undefined.

Programming Note

The vmodsq instruction performs a signed modulo operation on quadword elements. Ensure that the vector facility is enabled (MSR.VEC=1) to avoid exceptions. Be cautious with division by zero and handle cases where the dividend is 0x8000_0000_0000_0000_0000_0000_0000_0000 and the divisor is -1, as the result is undefined.

Example

vmodsq v1, v2, v3

Encoding

Binary Layout
4
0
VRT
6
VRA
11
VRB
16
 
Format VX-form
Opcode 0x1000070B
Extension VMX (AltiVec)
Registers Altered None

Operands

  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register