vmodsq

Vector Modulo Signed Quadword

vmodsq VRT,VRA,VRB

Performs signed modulo operation on quadword elements of two vector registers and stores the result in another vector register.

Details

Computes the signed modulo operation on quadword elements: each quadword element of VRA is divided by the corresponding quadword element of VRB and the remainder is stored in VRT. Division by zero results in undefined behavior. No condition flags are affected.

Pseudocode Operation

for i in 0 to 1 do
  dividend ← (s128)VRA[i*128:(i+1)*128-1]
  divisor ← (s128)VRB[i*128:(i+1)*128-1]
  VRT[i*128:(i+1)*128-1] ← dividend mod divisor
end for

Programming Note

The vmodsq instruction performs a signed modulo operation on quadword elements. Ensure that the vector facility is enabled (MSR.VEC=1) to avoid exceptions. Be cautious with division by zero and handle cases where the dividend is 0x8000_0000_0000_0000_0000_0000_0000_0000 and the divisor is -1, as the result is undefined.

Example

vmodsq v1, v2, v3

Encoding

Binary Layout
4
0
VRT
6
VRA
11
VRB
16
 
Format VX-form
Opcode 0x1000070B
Extension VMX (AltiVec)

Operands

  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register