xscvdpsp

VSX Scalar Convert Double-Precision to Single-Precision

xscvdpsp XT, XB

Converts a double-precision floating-point value in VSR[XB] to single-precision format and places the result into VSR[XT].

Details

The instruction converts the double-precision floating-point value from word element 0 of VSR[XB] to single-precision format. The result is placed into word elements 0 and 1 of VSR[XT], with word elements 2 and 3 set to zero.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src ← bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
rnd ← bfp_ROUND_TO_BFP32(FPSCR.RN, src)
result ← bfp32_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if xx_flag=1 then SetFX(FPSCR.XX)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
vex_flag ← FPSCR.VE & vxsnan_flag
if vex_flag=0 then do
    VSR[32×TX+T].word[0] ← result
    VSR[32×TX+T].word[1] ← result
    VSR[32×TX+T].word[2] ← 0x0000_0000
    VSR[32×TX+T].word[3] ← 0x0000_0000
    FPSCR.FPRF ← fprf_CLASS_BFP32(result)
    FPSCR.FR ← inc_flag
    FPSCR.FI ← xx_flag
end else do
    FPSCR.FI ← 0b0
end

Programming Note

['This instruction can be used to operate on a single-precision source operand.', 'Previous versions of the architecture allowed the contents of words 1, 2, and 3 of the result register to be undefined, however, all processors that support this instruction write the result into both words 0 and 1 of the result register, as is required by this version of the architecture.', 'If src is a SNaN, the result is src converted to a QNaN (i.e., bit 12 of src is set to 1). VXSNAN is set to 1.']

Example

xscvdpsp vs1, vs3

Encoding

Binary Layout
60
0
XT
11
0
16
XB
21
264
26
 
Format XX2-form
Opcode 0xF0000108
Extension VSX
Registers Altered FPSCR, FPRF, FR, FI, VXSNAN

Operands

  • XT
    Target
  • XB
    Source