vexpandwm

Vector Expand Word Mask

vexpandwm vD, vB

Expands bits from a GPR mask into a word-element vector.

Encoding

Binary Layout

0:5

VRT

6:10

11:15

VRB

16:20

1602

21:31

Format VX-form

Opcode 0x10020642

Extension VMX (AltiVec)

Operands

vD
Target
vB
Source
VRT
Target Vector Register
VRB
Source Vector Register

Example

vexpandwm vd, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vexpandwm, each word element of VSR[VRT+32] is set to all 0s or all 1s based on the value of bit 0 of the corresponding word element in VSR[VRB+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    let bmi be the contents of bit 0 of word element i of VSR[VRB+32]
    if bmi is equal to 0 then
        VSR[VRT+32].word[i] ←0xFFFF_FFFF
    else
        VSR[VRT+32].word[i] ←0x0000_0000
end

Programming Note

The vexpandwm instruction sets each word in the destination vector to all 1s or all 0s based on the least significant bit of the corresponding word in the source vector. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 32-bit words, so ensure proper alignment if manipulating data directly. The operation is performed on vectors, so verify that the input vectors are correctly loaded before execution.