dcbf

Data Cache Block Flush

dcbf RA,RB,L

Flushes the cache block from the data cache to main memory and invalidates it. Used for DMA coherency.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

21:30

Format X-form

Opcode 0x7C0000AC

Extension Base

Operands

RA
Base Address
RB
Index Address
L
Level of cache flush (0, 1, 3, 4, 6)
RT
Target General Purpose Register

Example

dcbf 0, r3

// Flush cache line at r3 to RAM.

Across architectures

Cache Line Flush : how x86, ARM, RISC-V, and PowerISA each do this.

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Data cache flush instruction that writes back and invalidates the cache block at effective address RA + RB to ensure coherency with main memory. Variants (dcbfl, dcbflp, dcbfps, dcbstps) control the level and scope of the flush operation. The L field (if present) selects the cache level. No general-purpose registers are modified and no condition flags are affected.

Operation

EA ← (RA) + (RB)
block_start ← EA & ~(cache_block_size - 1)
Flush_and_invalidate_cache_block(block_start, level=L)

Extended Mnemonics

Extended Mnemonic	Equivalent Instruction
dcbf RA,RB	dcbf RA,RB,0
dcbfl RA,RB	dcbf RA,RB,1
dcbflp RA,RB	dcbf RA,RB,3
dcbfps RA,RB	dcbf RA,RB,4
dcbstps RA,RB	dcbf RA,RB,6

Programming Note

dcbf serves as both a basic and an extended mnemonic. The Assembler will recognize a dcbf mnemonic with three operands as the basic form, and a dcbf mnemonic with two operands as the extended form. In the extended form the L operand is omitted and assumed to be 0. dcbf with L=1 can be used to provide a hint that a block in this processor’s data cache will not be reused soon. dcbf with L=3 can be used to flush a block from the processor’s primary data cache but reduce the latency of a subsequent access. For example, the block may be evicted from the primary data cache but a copy retained in a lower level of the cache hierarchy.