vpdepd

Vector Parallel Bits Deposit Doubleword

vpdepd vD, vA, vB

Deposits bits from source to target under control of a mask (Power10).

Encoding

Binary Layout

0:5

6:10

11:15

16:20

1485

21:31

Format VX-form

Opcode 0x100005CD

Extension VMX (AltiVec)

Operands

vD
Target
vA
Source
vB
Mask
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Mask Vector Register

Example

vpdepd vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The contents of bits in doubleword element i of VSR[VRT+32] corresponding to bits in doubleword element i of VSR[VRB+32] that contain a 0 are set to 0. The contents of the rightmost n bits of doubleword element i of VSR[VRA+32] are placed into doubleword element i of VSR[VRT+32] under control of the mask in doubleword element i of VSR[VRB+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    VSR[VRT+32].dword[i] ←0
    m ←0
    k ←0
    do while(m < 64)
        if VSR[VRB+32].dword[i].bit[63-m]=1 then do
            result ←VSR[VRA+32].dword[i].bit[63-k]
            VSR[VRT+32].dword[i].bit[63-m] ←result
            k ←k + 1
        end
        m ←m + 1
    end
end

Programming Note

The vpdepd instruction is used to deposit bits from one vector register into another based on a mask specified in a third vector register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The operation processes each doubleword element independently, and the alignment of the input vectors must be considered to avoid unexpected results. This instruction is particularly useful for bit manipulation tasks where selective depositing of bits is required.