vpksdss

Vector Pack Signed Doubleword Signed Saturate

vpksdss VRT,VRA,VRB

Packs signed doublewords from two vector registers into a single vector register with signed saturation.

Details

The instruction packs the contents of VSR[VRA+32] and VSR[VRB+32] into VSR[VRT+32], saturating signed values if they exceed the range of a 32-bit integer.

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
for i from 0 to 3 do
    VSR[VRT+32].word[i] ← si32_CLAMP(EXTS(VSR[VRA+32].dword[i]))
    if value > 2^31 - 1 then
        SAT is set to 1
    else if value < -(2^31) then
        SAT is set to 1

Programming Note

This instruction is useful for packing two 64-bit signed integers into a single 128-bit vector, with saturation applied to handle overflow. Ensure that the input vectors are correctly aligned and that the VSCR.SAT flag is checked after execution to determine if any values were saturated. This operation requires vector processing privileges.

Example

vpksdss v1, v2, v3

Encoding

Binary Layout
0
0
VRT
6
VRA
11
VRB
16
1486
 
Format VX-form
Opcode 0x100005CE
Extension VMX (AltiVec)
Registers Altered VSCR (SAT)

Operands

  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register