pmxvi4ger8

Prefixed Masked VSX Vector Integer 4-bit GER

pmxvi4ger8 AT, XA, XB, XMSK, YMSK

Masked 4-bit integer matrix multiply.

Encoding

Binary Layout

1

0

3

6

PMSK

8

XMSK

9

YMSK

14

0

32

59

38

AT

41

/

43

XA

48

XB

53

3

56

AX

57

BX

58

/

 

Format MMIRR-form

Opcode 0x07900000EC000118

Extension Prefixed

Operands

• AT
  Accumulator
• XA
  Src A
• XB
  Src B
• XMSK
  Mask A
• YMSK
  Mask B

Example

pmxvi4ger8 acc0, vs2, vs3, 15, 15

Related

More in Prefixed

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs a masked unsigned 4-bit integer matrix multiplication with rank-8 accumulation using separate row and column masks. This prefixed MMA instruction multiplies 4-bit elements from two VSX registers and adds the partial products to an MMA accumulator, with XMSK controlling which rows and YMSK controlling which columns participate. The result is treated as unsigned.

Operation

AT ← ACC[AT] + ((XA & XMSK) × (XB & YMSK))

Programming Note

The pmxvi4ger8 instruction is useful for performing masked vector integer operations, multiplying and accumulating products of signed integers from two vectors based on a mask. Ensure that the mask registers (XMSK, YMSK) are correctly set to control which elements are processed. The operation requires proper alignment of VSX registers, and results are clamped to 32-bit signed integers to prevent overflow. This instruction operates at privilege level 0.