vnegd

Vector Negate Doubleword

vnegd vD, vB

Negates each doubleword integer.

Encoding

Binary Layout

4

0:5

vD

6:10

0

11:15

vB

16:20

1604

21:31

 

Format VX-form

Opcode 0x10070602

Extension VMX (AltiVec)

Operands

• vD
  Target
• vB
  Source

Example

vnegd vd, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Computes the two's complement negation (0 - value) of each doubleword (64-bit) element in the source vector and writes the result to the target vector. No status register updates occur.

Operation

for i in 0 to 1:
  dword ← (VRB[i*64:(i+1)*64])
  VRT[i*64:(i+1)*64] ← -dword

Programming Note

The vnegd instruction is used to negate each doubleword element in a vector. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. This operation is performed on 64-bit elements, so ensure proper alignment and size of the vectors involved.