dcbzl

Data Cache Block Zero Long

dcbzl RA, RB

Zeros a cache block (implementation defined size).

Details

Zeros a cache block of implementation-defined size (typically larger than the standard dcbz 128-byte block) specified by the address computed as RA + RB. This instruction operates on the data cache and may affect cache coherency on multiprocessor systems. No condition or status registers are modified; cache operations are weakly ordered.

Pseudocode Operation

EA ← (RA) + (RB)
Zero cache block at EA with implementation-defined block size

Example

dcbzl r4, r5

Encoding

Binary Layout
31
0
/
6
RA
11
RB
16
1014
21
/
31
 
Format X-form
Opcode 0x7C0007EC
Extension Base

Operands

  • RA
    Base
  • RB
    Index