dcbzl

Data Cache Block Zero Long

dcbzl RA, RB

Zeros a cache block (implementation defined size).

Encoding

Binary Layout

31

0:5

/

6:10

RA

11:15

RB

16:20

1014

21:30

/

31

 

Format X-form

Opcode 0x7C0007EC

Extension Base

Operands

• RA
  Base
• RB
  Index

Example

dcbzl r4, r5

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Zeros a cache block of implementation-defined size (typically larger than the standard dcbz 128-byte block) specified by the address computed as RA + RB. This instruction operates on the data cache and may affect cache coherency on multiprocessor systems. No condition or status registers are modified; cache operations are weakly ordered.

Operation

EA ← (RA) + (RB)
Zero cache block at EA with implementation-defined block size