vclzlsbb

Vector Count Leading Zero Least Significant Bits Byte

vclzlsbb RA, vB

Counts the number of contiguous leading byte elements in VSR[VRB+32] having a zero least-significant bit.

Encoding

Binary Layout

4

0:5

RT

6:10

0

11:15

VRB

16:20

1538

21:31

 

Format VX-form

Opcode 0x10000602

Extension VMX (AltiVec)

Operands

• RA
  Target GPR
• vB
  Source
• RT
  Target General Purpose Register
• VRB
  Source Vector Register
• VRT
  Target Vector Register
• VSRC
  Source Vector Register

Example

vclzlsbb r4, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction counts the number of contiguous leading byte elements in VSR[VRB+32] that have a zero least-significant bit and places the count into GPR[RT].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
count ←0
do while count < 16
    if VSR[VRB+32].byte[count].bit[7]=1 then
        break
    count ←count + 1
end
GPR[RT] ←EXTZ64(count)

Programming Note

This instruction is useful for counting leading zero least significant bits in a vector register. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. The operation processes 16 bytes, and the result is stored in a general-purpose register. Be cautious of alignment requirements when accessing vector registers.