vcmpgtfp

Vector Compare Greater Than Floating-Point

vcmpgtfp VRT,VRA,VRB

Compares the contents of two vector registers and sets the target vector register based on whether each element is greater than the corresponding element in the other vector.

Encoding

Binary Layout

0:5

VRT

6:10

VRA

11:15

VRB

16:20

21:31

Format VC-form

Opcode 0x100002C6

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vcmpgtfp v1, v2, v3

Registers Altered

CR6

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vcmpgtfp, the contents of VSR[VRA+32] are compared to the contents of VSR[VRB+32]. The result is stored in VSR[VRT+32], with each word set to all 1s if the corresponding element in VSR[VRA+32] is greater than that in VSR[VRB+32], and all 0s otherwise.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
all_true ←1
all_false ←1
do i = 0 to 3
    src1 ←VSR[VRA+32].word[i]
    src2 ←VSR[VRB+32].word[i]
    if bool_COMPARE_GT_BFP32(src1,src2)=1 then
        VSR[VRT+32].word[i] ←0xFFFF_FFFF
        all_false ←0
    else
        all_true ←0
        VSR[VRT+32].word[i] ←0x0000_0000
end
if Rc=1 then
    CR.field[6] ←all_true || 0b0 || all_false || 0b0

Programming Note

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.