vcmpgtsw

Vector Compare Greater Than Signed Word

vcmpgtsw VRT,VRA,VRB
vcmpgtsw. VRT,VRA,VRB

Compares each word of two vector registers and sets the corresponding word in the target vector register to all 1s if the first operand is greater than the second, otherwise to all 0s.

Details

For vcmpgtsw, each word of VSR[VRA+32] is compared with the corresponding word of VSR[VRB+32]. If the signed integer value in the word element i of VSR[VRA+32] is greater than that in VSR[VRB+32], then the contents of word element i of VSR[VRT+32] are set to all 1s; otherwise, they are set to all 0s.

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
all_true ←1
all_false ←1
do i = 0 to 3
    src1 ←EXTS(VSR[VRA+32].word[i])
    src2 ←EXTS(VSR[VRB+32].word[i])
    if src1 > src2 then do
        VSR[VRT+32].word[i] ←0xFFFF_FFFF
        all_false ←0
    end
    else do
        VSR[VRT+32].word[i] ←0x0000_0000
        all_true ←0
    end
end
if Rc=1 then
    CR.field[6] ←all_true || 0b0 || all_false || 0b0

Programming Note

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.

Example

vcmpgtsw v1, v2, v3

Encoding

Binary Layout
4
0
VRT
6
VRA
11
VRB
16
Rc
21
 
Format VC-form
Opcode 0x10000386
Extension VMX (AltiVec)
Registers Altered CR6 (if Rc=1)

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register