vsel

Vector Select

vsel vD, vA, vB, vC

Bitwise selection. copies bits from vA if the corresponding bit in vC is 0, or from vB if vC is 1. (Like 'mux').

Encoding

Binary Layout

0:5

VRT

6:10

VRA

11:15

VRB

16:20

VRC

21:25

26:31

Format VA-form

Opcode 0x1000002A

Extension VMX (AltiVec)

Operands

vD
Target
vA
Source 0
vB
Source 1
vC
Control (Selector)
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register
VRC
Mask Vector Register

Example

vsel v1, v2, v3, v4

// Bitwise MUX.

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs bitwise selection from two source vectors based on a control vector. For each bit position, copies the bit from vA if the corresponding bit in vC is 0, or from vB if vC is 1. This is a three-operand mux operation. No condition registers or status flags are affected.

Operation

for i in 0 to 127:
  if vC[i] = 0 then vD[i] ← vA[i]
  else vD[i] ← vB[i]

Programming Note

The vsel instruction requires the Vector Facility to be enabled in the MSR. Ensure that VRA, VRB, and VRC are properly aligned and contain valid data. The result is stored in VRT, so ensure it is not being used elsewhere in your computation until the operation completes.