vrlq

Vector Rotate Left Quadword

vrlq vD, vA, vB

Rotates the contents of a vector register left by a specified number of bits.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

260

21:31

Format VX-form

Opcode 0x10000005

Extension VMX (AltiVec)

Operands

vD
Target
vA
Data
vB
Shift
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vrlq vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Rotates the 128-bit contents of the source vector left by the number of bits specified in the shift-count register and stores the result in the destination vector. The rotate amount is taken modulo 128; bits shifted out the left end wrap around to the right. No condition flags are affected; this is a VMX/AltiVec instruction.

Operation

shiftAmount ← vB[121:127] mod 128
vD[0:127] ← (vA[0:127] << shiftAmount) | (vA[0:127] >> (128 - shiftAmount))

Programming Note

The vrlq instruction is used to perform a left rotation of 128 bits in a vector register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The shift amount is determined by the upper 7 bits of another vector register, so ensure these bits are set correctly to avoid unexpected results.