vpkswss

Vector Pack Signed Word Signed Saturate

vpkswss vD, vA, vB

Packs signed words from two vector registers into a single vector register with signed saturation.

Details

The instruction vpkswss packs the contents of VSR[VRA+32] and VSR[VRB+32] into VSR[VRT+32], converting each word to a halfword with signed saturation.

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
vsrc.qword[0] ← VSR[VRA+32]
vsrc.qword[1] ← VSR[VRB+32]
do i = 0 to 7
    VSR[VRT+32].hword[i] ← si16_CLAMP(EXTS(vsrc.word[i]))
end

Programming Note

This instruction is commonly used for efficiently packing and saturating signed word values into halfwords. Ensure that the vector facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation involves extending each 32-bit word to 64 bits with sign extension, then clamping the result to fit within a 16-bit signed integer range. Be aware of potential saturation effects when dealing with values that exceed the halfword range.

Example

vpkswss vd, va, vb

Encoding

Binary Layout
4
0
vD
16
vA
21
vB
26
526
 
Format VX-form
Opcode 0x1000020E
Extension VMX (AltiVec)
Registers Altered VSCR.SAT

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register