vmuleud

Vector Multiply Even Unsigned Doubleword

vmuleud VRT,VRA,VRB

Multiplies the even doublewords of two vector registers and places the result in another vector register.

Encoding

Binary Layout

4

0:5

VRT

6:10

VRA

11:15

VRB

16:31

 

Format VX-form

Opcode 0x100002C8

Extension VMX (AltiVec)

Operands

• VRT
  Target Vector Register
• VRA
  Source Vector Register
• VRB
  Source Vector Register

Example

vmuleud v1, v2, v3

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction multiplies the unsigned integer values in the even doublewords of VSR[VRA+32] and VSR[VRB+32], and stores the 128-bit product in VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
src1 ←EXTZ(VSR[VRA+32].dword[0])
src2 ←EXTZ(VSR[VRB+32].dword[0])
VSR[VRT+32] ←CHOP128(src1 × src2)

Programming Note

This instruction is used for multiplying unsigned integers in the even doublewords of two vector registers and storing the 128-bit product. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. The operation is performed on the least significant doubleword of each input register, and the result is truncated to 128 bits before being stored.