vmuleub

Vector Multiply Even Unsigned Byte

vmuleub vD, vA, vB

Multiplies even-indexed bytes of two vector registers and stores the results in a destination vector register.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

520

21:31

Format VX-form

Opcode 0x10000208

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vmuleub vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vmuleub, each pair of even-indexed bytes from VSR[VRA+32] and VSR[VRB+32] are multiplied, and the 16-bit products are stored in halfwords of VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 7
    src1 ←EXTZ(VSR[VRA+32].byte[2×i])
    src2 ←EXTZ(VSR[VRB+32].byte[2×i])
    VSR[VRT+32].hword[i] ←CHOP16(src1 × src2)
end

Programming Note

This instruction multiplies even-indexed bytes from two vector registers and stores the 16-bit products in another vector register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. Be cautious of overflow, as the multiplication results are truncated to 16 bits.