pmxvi4ger8pp

Prefixed Masked VSX Vector Integer 4-bit GER Plus/Plus

pmxvi4ger8pp AT, XA, XB, XMSK, YMSK

Masked unsigned 4-bit integer matrix multiply.

Details

The pmxvi4ger8pp instruction performs a masked vector integer 4-bit GER (Generalized Rank-8 Update) operation on two VSX registers, accumulating the results into an accumulator register. It multiplies corresponding elements of the input vectors and adds them to the accumulator, with saturation if necessary.

Pseudocode Operation

For each integer value i from 0 to 3 and each integer value j from 0 to 3,
    If bit i of XMSK is equal to 1 and bit j of YMSK is equal to 1,
        prod0 ← EXTS(VSR[XA][i][0]) * EXTS(VSR[XB][j][0]) if PMSK[0] == 1 else 0
        prod1 ← EXTS(VSR[XA][i][1]) * EXTS(VSR[XB][j][1]) if PMSK[1] == 1 else 0
        sum ← prod0 + prod1
        result ← sum + ACC[AT][i][j]
        If result < -2^31, result ← -2^31 and SAT ← 1
        If result > 2^31 - 1, result ← 2^31 - 1 and SAT ← 1
        ACC[AT][i][j] ← result
    Else,
        ACC[AT][i][j] ← 0x0000_0000.

Programming Note

This instruction is useful for performing masked vectorized integer operations with saturation, ideal for applications requiring precise control over overflow conditions. Ensure that the mask registers (XMSK and YMSK) are correctly set to avoid unintended computations. The operation is performed at the user privilege level, but care must be taken to handle potential exceptions related to invalid register access or alignment issues. Performance may vary based on the specific data patterns and the effectiveness of the masking applied.

Example

pmxvi4ger8pp acc0, vs2, vs3, 15, 15

Encoding

Binary Layout
1
0
3
6
PMSK
8
XMSK
9
YMSK
14
0
32
59
38
AT
41
/
43
XA
48
XB
53
3
56
AX
57
BX
58
/
 
Format MMIRR-form
Opcode 0x06000000
Extension Prefixed
Registers Altered FPSCR

Operands

  • AT
    Accumulator
  • XA
    Src A
  • XB
    Src B
  • XMSK
    Mask A
  • YMSK
    Mask B