pmxvi4ger8pp
Prefixed Masked VSX Vector Integer 4-bit GER Plus/Plus
pmxvi4ger8pp AT, XA, XB, XMSK, YMSK
Masked unsigned 4-bit integer matrix multiply.
Encoding
Binary Layout
1
0
3
6
PMSK
8
XMSK
9
YMSK
14
0
32
59
38
AT
41
/
43
XA
48
XB
53
3
56
AX
57
BX
58
/
Operands
-
AT
Accumulator -
XA
Src A -
XB
Src B -
XMSK
Mask A -
YMSK
Mask B
Reference
View in PowerISA v3.1C Specification ↗
OPF Power ISA v3.1C
Description
Performs a masked unsigned 4-bit integer matrix multiplication with rank-8 accumulation and plus-signed saturation using separate row and column masks. This prefixed MMA instruction multiplies masked 4-bit elements from two VSX registers and accumulates the partial products into an MMA accumulator with unsigned saturation on overflow. XMSK controls row participation and YMSK controls column participation.
Operation
AT ← ACC[AT] + sat_u((XA & XMSK) × (XB & YMSK))Programming Note
This instruction is useful for performing masked vectorized integer operations with saturation, ideal for applications requiring precise control over overflow conditions. Ensure that the mask registers (XMSK and YMSK) are correctly set to avoid unintended computations. The operation is performed at the user privilege level, but care must be taken to handle potential exceptions related to invalid register access or alignment issues. Performance may vary based on the specific data patterns and the effectiveness of the masking applied.